// Copyright 2021 the V8 project authors. All rights reserved. // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following // disclaimer in the documentation and/or other materials provided // with the distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include #include #include "src/base/float16.h" #include "src/base/utils/random-number-generator.h" #include "src/codegen/assembler-inl.h" #include "src/codegen/macro-assembler.h" #include "src/diagnostics/disassembler.h" #include "src/execution/simulator.h" #include "src/heap/factory.h" #include "src/init/v8.h" #include "src/numbers/conversions-inl.h" #include "src/utils/utils.h" #include "test/common/value-helper.h" #include "test/unittests/assembler/test-helper-riscv64.h" #include "test/unittests/test-utils.h" namespace v8 { namespace internal { using AssemblerRISCV64Test = TestWithIsolate; // With 512-bit vectors, there are at most 64 elements. static_assert(kMaxRvvVLEN <= 512, "Unsupported VLEN"); const int kMaxElements = 64; // Define these function prototypes to match JSEntryFunction in execution.cc. using F1 = void*(int x, int p1, int p2, int p3, int p4); using F2 = void*(int x, int y, int p2, int p3, int p4); using F3 = void*(void* p, int p1, int p2, int p3, int p4); using F4 = void*(int64_t x, int64_t y, int64_t p2, int64_t p3, int64_t p4); using F5 = void*(void* p0, void* p1, int p2, int p3, int p4); #define MIN_VAL_IMM12 -(1 << 11) #define LARGE_INT_EXCEED_32_BIT 0x01C9'1075'0321'FB01LL #define LARGE_INT_UNDER_32_BIT 0x1234'5678 #define LARGE_UINT_EXCEED_32_BIT 0xFDCB'1234'A034'5691ULL #define __ assm. // Macro for concatenation #define CAT_(a, b) a##b #define CAT(a, b) CAT_(a, b) #define UTEST_R2_FORM_WITH_RES(instr_name, type, rs1_val, rs2_val, \ expected_res) \ TEST_F(AssemblerRISCV64Test, RISCV_UTEST_##instr_name) { \ auto fn = [](MacroAssembler& assm) { __ instr_name(a0, a0, a1); }; \ auto res = GenAndRunTest(rs1_val, rs2_val, fn); \ CHECK_EQ(expected_res, res); \ } // Generic macro for extension-specific tests with single feature #define UTEST_R2_FORM_WITH_RES_EXT(instr_name, type, rs1_val, rs2_val, \ expected_res, ext) \ TEST_F(AssemblerRISCV64Test, CAT(CAT(RISCV_UTEST_, instr_name), _##ext)) { \ if (!CpuFeatures::IsSupported(ext)) { \ return; \ } \ auto fn = [](MacroAssembler& assm) { __ instr_name(a0, a0, a1); }; \ auto res = GenAndRunTest(rs1_val, rs2_val, fn); \ CHECK_EQ(expected_res, res); \ } #define UTEST_R1_FORM_WITH_RES(instr_name, in_type, out_type, rs1_val, \ expected_res) \ TEST_F(AssemblerRISCV64Test, RISCV_UTEST_##instr_name) { \ auto fn = [](MacroAssembler& assm) { __ instr_name(a0, a0); }; \ auto res = GenAndRunTest(rs1_val, fn); \ CHECK_EQ(expected_res, res); \ } #define UTEST_R1_FORM_WITH_RES_EXT(instr_name, in_type, out_type, rs1_val, \ expected_res, ext) \ TEST_F(AssemblerRISCV64Test, CAT(CAT(RISCV_UTEST_, instr_name), _##ext)) { \ if (!CpuFeatures::IsSupported(ext)) { \ return; \ } \ auto fn = [](MacroAssembler& assm) { __ instr_name(a0, a0); }; \ auto res = GenAndRunTest(rs1_val, fn); \ CHECK_EQ(expected_res, res); \ } #define UTEST_R1_FORM_WITH_RES_C(instr_name, in_type, out_type, rs1_val, \ expected_res) \ TEST_F(AssemblerRISCV64Test, RISCV_UTEST_##instr_name) { \ if (!CpuFeatures::IsSupported(RVC)) { \ return; \ } \ \ auto fn = [](MacroAssembler& assm) { __ instr_name(a0, a0); }; \ auto res = GenAndRunTest(rs1_val, fn); \ CHECK_EQ(expected_res, res); \ } #define UTEST_I_FORM_WITH_RES(instr_name, type, rs1_val, imm12, expected_res) \ TEST_F(AssemblerRISCV64Test, RISCV_UTEST_##instr_name) { \ CHECK_EQ(is_intn(imm12, 12), true); \ auto fn = [](MacroAssembler& assm) { __ instr_name(a0, a0, imm12); }; \ auto res = GenAndRunTest(rs1_val, fn); \ CHECK_EQ(expected_res, res); \ } #define UTEST_I_FORM_WITH_RES_EXT(instr_name, type, rs1_val, imm12, \ expected_res, ext) \ TEST_F(AssemblerRISCV64Test, CAT(CAT(RISCV_UTEST_, instr_name), _##ext)) { \ if (!CpuFeatures::IsSupported(ext)) { \ return; \ } \ CHECK_EQ(is_intn(imm12, 12), true); \ auto fn = [](MacroAssembler& assm) { __ instr_name(a0, a0, imm12); }; \ auto res = GenAndRunTest(rs1_val, fn); \ CHECK_EQ(expected_res, res); \ } #define UTEST_AMO_WITH_RES(instr_name, aq, rl, inout_type, rs1_val, rs2_val, \ expected_res) \ TEST_F(AssemblerRISCV64Test, RISCV_UTEST_##instr_name) { \ auto fn = [](MacroAssembler& assm) { __ instr_name(aq, rl, a1, a0, a2); }; \ auto res = \ GenAndRunTestForAMO(rs1_val, rs2_val, fn); \ CHECK_EQ(expected_res, res); \ } #define UTEST_LOAD_STORE(ldname, stname, value_type, value) \ TEST_F(AssemblerRISCV64Test, RISCV_UTEST_##stname##ldname) { \ auto fn = [](MacroAssembler& assm) { \ __ stname(a1, a0, 0); \ __ ldname(a0, a0, 0); \ }; \ GenAndRunTestForLoadStore(value, fn); \ } // Since f.Call() is implemented as vararg calls and RISCV calling convention // passes all vararg arguments and returns (including floats) in GPRs, we have // to move from GPR to FPR and back in all floating point tests #define UTEST_LOAD_STORE_F(ldname, stname, value_type, store_value) \ TEST_F(AssemblerRISCV64Test, RISCV_UTEST_##stname##ldname) { \ DCHECK(std::is_floating_point_v); \ \ auto fn = [](MacroAssembler& assm) { \ __ stname(fa0, a0, 0); \ __ ldname(fa0, a0, 0); \ }; \ GenAndRunTestForLoadStore(store_value, fn); \ } #define UTEST_LR_SC(ldname, stname, aq, rl, value_type, value) \ TEST_F(AssemblerRISCV64Test, RISCV_UTEST_##stname##ldname) { \ auto fn = [](MacroAssembler& assm) { \ __ ldname(aq, rl, a1, a0); \ __ stname(aq, rl, a0, a0, a1); \ }; \ GenAndRunTestForLRSC(value, fn); \ } #define UTEST_R1_FORM_WITH_RES_F(instr_name, type, rs1_fval, expected_fres) \ TEST_F(AssemblerRISCV64Test, RISCV_UTEST_##instr_name) { \ DCHECK(std::is_floating_point_v); \ \ auto fn = [](MacroAssembler& assm) { __ instr_name(fa0, fa0); }; \ auto res = GenAndRunTest(rs1_fval, fn); \ CHECK_EQ(expected_fres, res); \ } #define UTEST_R2_FORM_WITH_RES_F(instr_name, type, rs1_fval, rs2_fval, \ expected_fres) \ TEST_F(AssemblerRISCV64Test, RISCV_UTEST_##instr_name) { \ DCHECK(std::is_floating_point_v); \ \ auto fn = [](MacroAssembler& assm) { __ instr_name(fa0, fa0, fa1); }; \ auto res = GenAndRunTest(rs1_fval, rs2_fval, fn); \ CHECK_EQ(expected_fres, res); \ } #define UTEST_R3_FORM_WITH_RES_F(instr_name, type, rs1_fval, rs2_fval, \ rs3_fval, expected_fres) \ TEST_F(AssemblerRISCV64Test, RISCV_UTEST_##instr_name) { \ DCHECK(std::is_floating_point_v); \ \ auto fn = [](MacroAssembler& assm) { __ instr_name(fa0, fa0, fa1, fa2); }; \ auto res = GenAndRunTest(rs1_fval, rs2_fval, rs3_fval, fn); \ CHECK_EQ(expected_fres, res); \ } #define UTEST_COMPARE_WITH_RES_F(instr_name, input_type, rs1_fval, rs2_fval, \ expected_res) \ TEST_F(AssemblerRISCV64Test, RISCV_UTEST_##instr_name) { \ auto fn = [](MacroAssembler& assm) { __ instr_name(a0, fa0, fa1); }; \ auto res = GenAndRunTest(rs1_fval, rs2_fval, fn); \ CHECK_EQ(expected_res, res); \ } #define UTEST_CONV_F_FROM_I(instr_name, input_type, output_type, rs1_val, \ expected_fres) \ TEST_F(AssemblerRISCV64Test, RISCV_UTEST_##instr_name) { \ DCHECK(std::is_integral_v && \ std::is_floating_point_v); \ \ auto fn = [](MacroAssembler& assm) { __ instr_name(fa0, a0); }; \ auto res = GenAndRunTest(rs1_val, fn); \ CHECK_EQ(expected_fres, res); \ } #define UTEST_CONV_I_FROM_F(instr_name, input_type, output_type, \ rounding_mode, rs1_fval, expected_res) \ TEST_F(AssemblerRISCV64Test, RISCV_UTEST_##instr_name) { \ DCHECK(std::is_floating_point_v && \ std::is_integral_v); \ \ auto fn = [](MacroAssembler& assm) { \ __ instr_name(a0, fa0, rounding_mode); \ }; \ auto res = GenAndRunTest(rs1_fval, fn); \ CHECK_EQ(expected_res, res); \ } \ \ TEST_F(AssemblerRISCV64Test, RISCV_UTEST_dyn_##instr_name) { \ DCHECK(std::is_floating_point_v && \ std::is_integral_v); \ \ auto fn = [](MacroAssembler& assm) { \ __ csrrwi(t0, csr_frm, rounding_mode); \ __ instr_name(a0, fa0, DYN); \ __ csrw(csr_frm, t0); \ }; \ auto res = GenAndRunTest(rs1_fval, fn); \ CHECK_EQ(expected_res, res); \ } #define UTEST_CONV_F_FROM_F(instr_name, input_type, output_type, rs1_val, \ expected_fres) \ TEST_F(AssemblerRISCV64Test, RISCV_UTEST_##instr_name) { \ auto fn = [](MacroAssembler& assm) { __ instr_name(fa0, fa0); }; \ auto res = GenAndRunTest(rs1_val, fn); \ CHECK_EQ(expected_fres, res); \ } #define UTEST_CSRI(csr_reg, csr_write_val, csr_set_clear_val) \ TEST_F(AssemblerRISCV64Test, RISCV_UTEST_CSRI_##csr_reg) { \ CHECK_EQ(is_uint5(csr_write_val) && is_uint5(csr_set_clear_val), true); \ \ int64_t expected_res = 111; \ Label exit, error; \ auto fn = [&exit, &error, expected_res](MacroAssembler& assm) { \ __ csrr(t1, csr_reg); \ /* test csr-write and csr-read */ \ __ csrwi(csr_reg, csr_write_val); \ __ csrr(a0, csr_reg); \ __ RV_li(a1, csr_write_val); \ __ bne(a0, a1, &error); \ /* test csr_set */ \ __ csrsi(csr_reg, csr_set_clear_val); \ __ csrr(a0, csr_reg); \ __ RV_li(a1, (csr_write_val) | (csr_set_clear_val)); \ __ bne(a0, a1, &error); \ /* test csr_clear */ \ __ csrci(csr_reg, csr_set_clear_val); \ __ csrr(a0, csr_reg); \ __ RV_li(a1, (csr_write_val) & (~(csr_set_clear_val))); \ __ bne(a0, a1, &error); \ /* everyhing runs correctly, return 111 */ \ __ RV_li(a0, expected_res); \ __ j(&exit); \ \ __ bind(&error); \ /* got an error, return 666 */ \ __ RV_li(a0, 666); \ \ __ bind(&exit); \ __ csrw(csr_reg, t1); \ }; \ auto res = GenAndRunTest(fn); \ CHECK_EQ(expected_res, res); \ } #define UTEST_CSR(csr_reg, csr_write_val, csr_set_clear_val) \ TEST_F(AssemblerRISCV64Test, RISCV_UTEST_CSR_##csr_reg) { \ Label exit, error; \ int64_t expected_res = 111; \ auto fn = [&exit, &error, expected_res](MacroAssembler& assm) { \ __ csrr(t1, csr_reg); \ /* test csr-write and csr-read */ \ __ RV_li(t0, csr_write_val); \ __ csrw(csr_reg, t0); \ __ csrr(a0, csr_reg); \ __ RV_li(a1, csr_write_val); \ __ bne(a0, a1, &error); \ /* test csr_set */ \ __ RV_li(t0, csr_set_clear_val); \ __ csrs(csr_reg, t0); \ __ csrr(a0, csr_reg); \ __ RV_li(a1, (csr_write_val) | (csr_set_clear_val)); \ __ bne(a0, a1, &error); \ /* test csr_clear */ \ __ RV_li(t0, csr_set_clear_val); \ __ csrc(csr_reg, t0); \ __ csrr(a0, csr_reg); \ __ RV_li(a1, (csr_write_val) & (~(csr_set_clear_val))); \ __ bne(a0, a1, &error); \ /* everyhing runs correctly, return 111 */ \ __ RV_li(a0, expected_res); \ __ j(&exit); \ \ __ bind(&error); \ /* got an error, return 666 */ \ __ RV_li(a0, 666); \ \ __ bind(&exit); \ __ csrw(csr_reg, t1); \ }; \ \ auto res = GenAndRunTest(fn); \ CHECK_EQ(expected_res, res); \ } #define UTEST_R2_FORM_WITH_OP(instr_name, type, rs1_val, rs2_val, tested_op) \ UTEST_R2_FORM_WITH_RES(instr_name, type, rs1_val, rs2_val, \ ((rs1_val)tested_op(rs2_val))) #define UTEST_I_FORM_WITH_OP(instr_name, type, rs1_val, imm12, tested_op) \ UTEST_I_FORM_WITH_RES(instr_name, type, rs1_val, imm12, \ ((rs1_val)tested_op(imm12))) #define UTEST_R2_FORM_WITH_OP_F(instr_name, type, rs1_fval, rs2_fval, \ tested_op) \ UTEST_R2_FORM_WITH_RES_F(instr_name, type, rs1_fval, rs2_fval, \ ((rs1_fval)tested_op(rs2_fval))) #define UTEST_COMPARE_WITH_OP_F(instr_name, input_type, rs1_fval, rs2_fval, \ tested_op) \ UTEST_COMPARE_WITH_RES_F(instr_name, input_type, rs1_fval, rs2_fval, \ ((rs1_fval)tested_op(rs2_fval))) // -- test load-store -- UTEST_LOAD_STORE(ld, sd, int64_t, 0xFBB10A9C12345678) // due to sign-extension of lw // instruction, value-to-stored must have // its 32th least significant bit be 0 UTEST_LOAD_STORE(lw, sw, int32_t, 0x456AF894) // set the 32th least significant bit of // value-to-store to 1 to test // zero-extension by lwu UTEST_LOAD_STORE(lwu, sw, uint32_t, 0x856AF894) // due to sign-extension of lh // instruction, value-to-stored must have // its 16th least significant bit be 0 UTEST_LOAD_STORE(lh, sh, int32_t, 0x7894) // set the 16th least significant bit of // value-to-store to 1 to test // zero-extension by lhu UTEST_LOAD_STORE(lhu, sh, uint32_t, 0xF894) // due to sign-extension of lb // instruction, value-to-stored must have // its 8th least significant bit be 0 UTEST_LOAD_STORE(lb, sb, int32_t, 0x54) // set the 8th least significant bit of // value-to-store to 1 to test // zero-extension by lbu UTEST_LOAD_STORE(lbu, sb, uint32_t, 0x94) // -- arithmetic w/ immediate -- UTEST_I_FORM_WITH_OP(addi, int64_t, LARGE_INT_EXCEED_32_BIT, MIN_VAL_IMM12, +) UTEST_I_FORM_WITH_OP(slti, int64_t, LARGE_INT_EXCEED_32_BIT, MIN_VAL_IMM12, <) UTEST_I_FORM_WITH_OP(sltiu, uint64_t, LARGE_UINT_EXCEED_32_BIT, 0x4FB, <) UTEST_I_FORM_WITH_OP(xori, int64_t, LARGE_INT_EXCEED_32_BIT, MIN_VAL_IMM12, ^) UTEST_I_FORM_WITH_OP(ori, int64_t, LARGE_INT_EXCEED_32_BIT, MIN_VAL_IMM12, |) UTEST_I_FORM_WITH_OP(andi, int64_t, LARGE_INT_EXCEED_32_BIT, MIN_VAL_IMM12, &) UTEST_I_FORM_WITH_OP(slli, int64_t, 0x1234'5678ULL, 33, <<) UTEST_I_FORM_WITH_OP(srli, int64_t, 0x8234'5678'0000'0000ULL, 33, >>) UTEST_I_FORM_WITH_OP(srai, int64_t, -0x1234'5678'0000'0000LL, 33, >>) // -- arithmetic -- UTEST_R2_FORM_WITH_OP(add, int64_t, LARGE_INT_EXCEED_32_BIT, MIN_VAL_IMM12, +) UTEST_R2_FORM_WITH_OP(sub, int64_t, LARGE_INT_EXCEED_32_BIT, MIN_VAL_IMM12, -) UTEST_R2_FORM_WITH_OP(slt, int64_t, MIN_VAL_IMM12, LARGE_INT_EXCEED_32_BIT, <) UTEST_R2_FORM_WITH_OP(sltu, uint64_t, 0x4FB, LARGE_UINT_EXCEED_32_BIT, <) UTEST_R2_FORM_WITH_OP(xor_, int64_t, LARGE_INT_EXCEED_32_BIT, MIN_VAL_IMM12, ^) UTEST_R2_FORM_WITH_OP(or_, int64_t, LARGE_INT_EXCEED_32_BIT, MIN_VAL_IMM12, |) UTEST_R2_FORM_WITH_OP(and_, int64_t, LARGE_INT_EXCEED_32_BIT, MIN_VAL_IMM12, &) UTEST_R2_FORM_WITH_OP(sll, int64_t, 0x12345678ULL, 33, <<) UTEST_R2_FORM_WITH_OP(srl, int64_t, 0x8234567800000000ULL, 33, >>) UTEST_R2_FORM_WITH_OP(sra, int64_t, -0x1234'5678'0000'0000LL, 33, >>) // -- Memory fences -- // void fence(uint8_t pred, uint8_t succ); // void fence_tso(); // -- Environment call / break -- // void ecall(); // void ebreak(); // void unimp(); // -- CSR -- UTEST_CSRI(csr_frm, DYN, RUP) UTEST_CSRI(csr_fflags, kInexact | kInvalidOperation, kInvalidOperation) UTEST_CSRI(csr_fcsr, kDivideByZero | kFPUOverflow, kUnderflow) UTEST_CSR(csr_frm, DYN, RUP) UTEST_CSR(csr_fflags, kInexact | kInvalidOperation, kInvalidOperation) UTEST_CSR(csr_fcsr, kDivideByZero | kFPUOverflow | (RDN << kFcsrFrmShift), kUnderflow | (RNE << kFcsrFrmShift)) // -- RV64I -- UTEST_I_FORM_WITH_OP(addiw, int32_t, LARGE_INT_UNDER_32_BIT, MIN_VAL_IMM12, +) UTEST_I_FORM_WITH_OP(slliw, int32_t, 0x12345678U, 12, <<) UTEST_I_FORM_WITH_OP(srliw, int32_t, 0x82345678U, 12, >>) UTEST_I_FORM_WITH_OP(sraiw, int32_t, -123, 12, >>) UTEST_R2_FORM_WITH_OP(addw, int32_t, LARGE_INT_UNDER_32_BIT, MIN_VAL_IMM12, +) UTEST_R2_FORM_WITH_OP(subw, int32_t, LARGE_INT_UNDER_32_BIT, MIN_VAL_IMM12, -) UTEST_R2_FORM_WITH_OP(sllw, int32_t, 0x12345678U, 12, <<) UTEST_R2_FORM_WITH_OP(srlw, int32_t, 0x82345678U, 12, >>) UTEST_R2_FORM_WITH_OP(sraw, int32_t, -123, 12, >>) // -- RV32M Standard Extension -- UTEST_R2_FORM_WITH_OP(mul, int64_t, 0x0F945001L, MIN_VAL_IMM12, *) UTEST_R2_FORM_WITH_RES(mulh, int64_t, 0x1234567800000000LL, -0x1234'5617'0000'0000LL, 0x12345678LL * -0x1234'5617LL) UTEST_R2_FORM_WITH_RES(mulhu, int64_t, 0x1234'5678'0000'0000ULL, 0xF896'7021'0000'0000ULL, 0x1234'5678ULL * 0xF896'7021ULL) UTEST_R2_FORM_WITH_RES(mulhsu, int64_t, -0x1234'56780000'0000LL, 0xF234'5678'0000'0000ULL, static_cast(-0x1234'5678LL * 0xF234'5678ULL)) UTEST_R2_FORM_WITH_OP(div, int64_t, LARGE_INT_EXCEED_32_BIT, MIN_VAL_IMM12, /) UTEST_R2_FORM_WITH_OP(divu, uint64_t, LARGE_UINT_EXCEED_32_BIT, 100, /) UTEST_R2_FORM_WITH_OP(rem, int64_t, LARGE_INT_EXCEED_32_BIT, MIN_VAL_IMM12, %) UTEST_R2_FORM_WITH_OP(remu, uint64_t, LARGE_UINT_EXCEED_32_BIT, 100, %) // -- RV64M Standard Extension (in addition to RV32M) -- UTEST_R2_FORM_WITH_OP(mulw, int32_t, -20, 56, *) UTEST_R2_FORM_WITH_OP(divw, int32_t, 200, -10, /) UTEST_R2_FORM_WITH_OP(divuw, uint32_t, 1000, 100, /) UTEST_R2_FORM_WITH_OP(remw, int32_t, 1234, -91, %) UTEST_R2_FORM_WITH_OP(remuw, uint32_t, 1234, 43, %) // -- RV32A Standard Extension -- UTEST_LR_SC(lr_w, sc_w, false, false, int32_t, 0xFBB1A75C) UTEST_AMO_WITH_RES(amoswap_w, false, false, uint32_t, 0xFBB1A75C, 0xA75C0A9C, (uint32_t)0xA75C0A9C) UTEST_AMO_WITH_RES(amoadd_w, false, false, uint32_t, 0xFBB1A75C, 0xA75C0A9C, (uint32_t)0xFBB1A75C + (uint32_t)0xA75C0A9C) UTEST_AMO_WITH_RES(amoxor_w, false, false, uint32_t, 0xFBB1A75C, 0xA75C0A9C, (uint32_t)0xFBB1A75C ^ (uint32_t)0xA75C0A9C) UTEST_AMO_WITH_RES(amoand_w, false, false, uint32_t, 0xFBB1A75C, 0xA75C0A9C, (uint32_t)0xFBB1A75C & (uint32_t)0xA75C0A9C) UTEST_AMO_WITH_RES(amoor_w, false, false, uint32_t, 0xFBB1A75C, 0xA75C0A9C, (uint32_t)0xFBB1A75C | (uint32_t)0xA75C0A9C) UTEST_AMO_WITH_RES(amomin_w, false, false, int32_t, 0xFBB1A75C, 0xA75C0A9C, std::min((int32_t)0xFBB1A75C, (int32_t)0xA75C0A9C)) UTEST_AMO_WITH_RES(amomax_w, false, false, int32_t, 0xFBB1A75C, 0xA75C0A9C, std::max((int32_t)0xFBB1A75C, (int32_t)0xA75C0A9C)) UTEST_AMO_WITH_RES(amominu_w, false, false, uint32_t, 0xFBB1A75C, 0xA75C0A9C, std::min((uint32_t)0xFBB1A75C, (uint32_t)0xA75C0A9C)) UTEST_AMO_WITH_RES(amomaxu_w, false, false, uint32_t, 0xFBB1A75C, 0xA75C0A9C, std::max((uint32_t)0xFBB1A75C, (uint32_t)0xA75C0A9C)) // -- RV64A Standard Extension (in addition to RV32A) -- UTEST_LR_SC(lr_d, sc_d, false, false, int64_t, 0xFBB10A9Cbfb76aa6) UTEST_AMO_WITH_RES(amoswap_d, false, false, int64_t, 0xFBB10A9Cbfb76aa6, 0x284ff922346ad35c, (int64_t)0x284ff922346ad35c) UTEST_AMO_WITH_RES(amoadd_d, false, false, int64_t, 0xFBB10A9Cbfb76aa6, 0x284ff922346ad35c, (int64_t)0xFBB10A9Cbfb76aa6 + (int64_t)0x284ff922346ad35c) UTEST_AMO_WITH_RES(amoxor_d, false, false, int64_t, 0xFBB10A9Cbfb76aa6, 0x284ff922346ad35c, (int64_t)0xFBB10A9Cbfb76aa6 ^ (int64_t)0x284ff922346ad35c) UTEST_AMO_WITH_RES(amoand_d, false, false, int64_t, 0xFBB10A9Cbfb76aa6, 0x284ff922346ad35c, (int64_t)0xFBB10A9Cbfb76aa6 & (int64_t)0x284ff922346ad35c) UTEST_AMO_WITH_RES(amoor_d, false, false, int64_t, 0xFBB10A9Cbfb76aa6, 0x284ff922346ad35c, (int64_t)0xFBB10A9Cbfb76aa6 | (int64_t)0x284ff922346ad35c) UTEST_AMO_WITH_RES(amomin_d, false, false, int64_t, 0xFBB10A9Cbfb76aa6, 0x284ff922346ad35c, std::min((int64_t)0xFBB10A9Cbfb76aa6, (int64_t)0x284ff922346ad35c)) UTEST_AMO_WITH_RES(amomax_d, false, false, int64_t, 0xFBB10A9Cbfb76aa6, 0x284ff922346ad35c, std::max((int64_t)0xFBB10A9Cbfb76aa6, (int64_t)0x284ff922346ad35c)) UTEST_AMO_WITH_RES(amominu_d, false, false, uint64_t, 0xFBB10A9Cbfb76aa6, 0x284ff922346ad35c, std::min((uint64_t)0xFBB10A9Cbfb76aa6, (uint64_t)0x284ff922346ad35c)) UTEST_AMO_WITH_RES(amomaxu_d, false, false, uint64_t, 0xFBB10A9Cbfb76aa6, 0x284ff922346ad35c, std::max((uint64_t)0xFBB10A9Cbfb76aa6, (uint64_t)0x284ff922346ad35c)) // RV64B UTEST_R2_FORM_WITH_RES_EXT( sh1add, int64_t, LARGE_INT_EXCEED_32_BIT, LARGE_UINT_EXCEED_32_BIT, ((LARGE_UINT_EXCEED_32_BIT) + (LARGE_INT_EXCEED_32_BIT << 1)), ZBA) UTEST_R2_FORM_WITH_RES_EXT( sh2add, int64_t, LARGE_INT_EXCEED_32_BIT, LARGE_UINT_EXCEED_32_BIT, ((LARGE_UINT_EXCEED_32_BIT) + (LARGE_INT_EXCEED_32_BIT << 2)), ZBA) UTEST_R2_FORM_WITH_RES_EXT( sh3add, int64_t, LARGE_INT_EXCEED_32_BIT, LARGE_UINT_EXCEED_32_BIT, ((LARGE_UINT_EXCEED_32_BIT) + (LARGE_INT_EXCEED_32_BIT << 3)), ZBA) UTEST_R2_FORM_WITH_RES_EXT(sh1adduw, int64_t, 0x13f42, 1, ((1) + (uint32_t(0x13f42) << 1)), ZBA) UTEST_R2_FORM_WITH_RES_EXT(sh2adduw, int64_t, 0x13f42, LARGE_UINT_EXCEED_32_BIT, int64_t((LARGE_UINT_EXCEED_32_BIT) + (uint32_t(0x13f42) << 2)), ZBA) UTEST_R2_FORM_WITH_RES_EXT(sh3adduw, int64_t, LARGE_INT_EXCEED_32_BIT, LARGE_UINT_EXCEED_32_BIT, int64_t((LARGE_UINT_EXCEED_32_BIT) + (uint32_t(LARGE_INT_EXCEED_32_BIT) << 3)), ZBA) UTEST_R2_FORM_WITH_RES_EXT(adduw, int64_t, LARGE_INT_EXCEED_32_BIT, LARGE_UINT_EXCEED_32_BIT, int64_t((LARGE_UINT_EXCEED_32_BIT) + (uint32_t(LARGE_INT_EXCEED_32_BIT))), ZBA) UTEST_I_FORM_WITH_RES_EXT(slliuw, int64_t, LARGE_INT_EXCEED_32_BIT, 10, (int64_t(uint32_t(LARGE_INT_EXCEED_32_BIT))) << 10, ZBA) UTEST_R2_FORM_WITH_RES_EXT( andn, int64_t, LARGE_INT_EXCEED_32_BIT, LARGE_UINT_EXCEED_32_BIT, ((LARGE_INT_EXCEED_32_BIT) & (~LARGE_UINT_EXCEED_32_BIT)), ZBB) UTEST_R2_FORM_WITH_RES_EXT( orn, int64_t, LARGE_INT_EXCEED_32_BIT, LARGE_UINT_EXCEED_32_BIT, ((LARGE_INT_EXCEED_32_BIT) | (~LARGE_UINT_EXCEED_32_BIT)), ZBB) UTEST_R2_FORM_WITH_RES_EXT( xnor, int64_t, LARGE_INT_EXCEED_32_BIT, LARGE_UINT_EXCEED_32_BIT, int64_t(~(LARGE_INT_EXCEED_32_BIT ^ LARGE_UINT_EXCEED_32_BIT)), ZBB) UTEST_R1_FORM_WITH_RES_EXT(clz, int64_t, int64_t, 0b000011000100000000000, 47, ZBB) UTEST_R1_FORM_WITH_RES_EXT(ctz, int64_t, int64_t, 0b000011000100000000000, 11, ZBB) UTEST_R1_FORM_WITH_RES_EXT(clzw, int64_t, int64_t, 0b000011000100000000000, 15, ZBB) UTEST_R1_FORM_WITH_RES_EXT(ctzw, int64_t, int64_t, 0b000011000100000000000, 11, ZBB) UTEST_R1_FORM_WITH_RES_EXT(cpop, int64_t, int64_t, 0b000011000100000000000, 3, ZBB) UTEST_R1_FORM_WITH_RES_EXT(cpopw, int64_t, int64_t, 0b000011000100000000011, 5, ZBB) UTEST_R2_FORM_WITH_RES_EXT(max, int64_t, -1012, 3456, 3456, ZBB) UTEST_R2_FORM_WITH_RES_EXT(min, int64_t, -1012, 3456, -1012, ZBB) UTEST_R2_FORM_WITH_RES_EXT(maxu, uint64_t, -1012, 3456, uint64_t(-1012), ZBB) UTEST_R2_FORM_WITH_RES_EXT(minu, uint64_t, -1012, 3456, 3456, ZBB) UTEST_R1_FORM_WITH_RES_EXT(sextb, int64_t, int64_t, 0xB080, int64_t(0xffffffffffffff80), ZBB) UTEST_R1_FORM_WITH_RES_EXT(sexth, int64_t, int64_t, 0xB080, int64_t(0xffffffffffffb080), ZBB) UTEST_R1_FORM_WITH_RES_EXT(zexth, int64_t, int64_t, 0xB080, 0xB080, ZBB) UTEST_R2_FORM_WITH_RES_EXT(rol, uint64_t, 16, 2, 64, ZBB) UTEST_R2_FORM_WITH_RES_EXT(rolw, uint32_t, 16, 2, 64, ZBB) UTEST_R2_FORM_WITH_RES_EXT(ror, uint64_t, 16, 2, 4, ZBB) UTEST_R2_FORM_WITH_RES_EXT(rorw, uint32_t, 16, 2, 4, ZBB) UTEST_I_FORM_WITH_RES_EXT(rori, int64_t, 16, 2, 4, ZBB) UTEST_I_FORM_WITH_RES_EXT(roriw, int32_t, 16, 2, 4, ZBB) UTEST_R1_FORM_WITH_RES_EXT(orcb, int64_t, uint64_t, 0xFF00011010010011, 0xFF00FFFFFFFF00FF, ZBB) UTEST_R1_FORM_WITH_RES_EXT(rev8, uint64_t, uint64_t, 0x1234567890ABCDEF, 0xEFCDAB9078563412, ZBB) UTEST_R2_FORM_WITH_RES_EXT(bclr, int64_t, 0x13f62, 5, 0x13f42, ZBS) UTEST_I_FORM_WITH_RES_EXT(bclri, int64_t, 0x2013F6213F62, 45, 0x13f6213f62, ZBS) UTEST_R2_FORM_WITH_RES_EXT(bext, int64_t, 0x13f62, 5, 1, ZBS) UTEST_I_FORM_WITH_RES_EXT(bexti, int64_t, 0x2013F6213F62, 45, 1, ZBS) UTEST_R2_FORM_WITH_RES_EXT(binv, int64_t, 0x13f62, 5, 0x13f42, ZBS) UTEST_I_FORM_WITH_RES_EXT(binvi, int64_t, 0x13f6213f62, 45, 0x2013F6213F62, ZBS) UTEST_R2_FORM_WITH_RES_EXT(bset, int64_t, 0x13f42, 5, 0x13f62, ZBS) UTEST_I_FORM_WITH_RES_EXT(bseti, int64_t, 0x13f6213f62, 45, 0x2013F6213F62, ZBS) // -- RV32F Standard Extension -- UTEST_LOAD_STORE_F(flw, fsw, float, -2345.678f) UTEST_R2_FORM_WITH_OP_F(fadd_s, float, -1012.01f, 3456.13f, +) UTEST_R2_FORM_WITH_OP_F(fsub_s, float, -1012.01f, 3456.13f, -) UTEST_R2_FORM_WITH_OP_F(fmul_s, float, -10.01f, 56.13f, *) UTEST_R2_FORM_WITH_OP_F(fdiv_s, float, -10.01f, 34.13f, /) UTEST_R1_FORM_WITH_RES_F(fsqrt_s, float, 34.13f, sqrtf(34.13f)) UTEST_R2_FORM_WITH_RES_F(fmin_s, float, -1012.0f, 3456.13f, -1012.0f) UTEST_R2_FORM_WITH_RES_F(fmax_s, float, -1012.0f, 3456.13f, 3456.13f) UTEST_R3_FORM_WITH_RES_F(fmadd_s, float, 67.56f, -1012.01f, 3456.13f, std::fma(67.56f, -1012.01f, 3456.13f)) UTEST_R3_FORM_WITH_RES_F(fmsub_s, float, 67.56f, -1012.01f, 3456.13f, std::fma(67.56f, -1012.01f, -3456.13f)) UTEST_R3_FORM_WITH_RES_F(fnmsub_s, float, 67.56f, -1012.01f, 3456.13f, -std::fma(67.56f, -1012.01f, -3456.13f)) UTEST_R3_FORM_WITH_RES_F(fnmadd_s, float, 67.56f, -1012.01f, 3456.13f, -std::fma(67.56f, -1012.01f, 3456.13f)) UTEST_COMPARE_WITH_OP_F(feq_s, float, -3456.56, -3456.56, ==) UTEST_COMPARE_WITH_OP_F(flt_s, float, -3456.56, -3456.56, <) UTEST_COMPARE_WITH_OP_F(fle_s, float, -3456.56, -3456.56, <=) UTEST_CONV_F_FROM_I(fcvt_s_w, int32_t, float, -100, (float)(-100)) UTEST_CONV_F_FROM_I(fcvt_s_wu, uint32_t, float, std::numeric_limits::max(), (float)(std::numeric_limits::max())) UTEST_CONV_I_FROM_F(fcvt_w_s, float, int32_t, RMM, -100.5f, -101) UTEST_CONV_I_FROM_F(fcvt_wu_s, float, uint32_t, RUP, 256.1f, 257) UTEST_R2_FORM_WITH_RES_F(fsgnj_s, float, -100.0f, 200.0f, 100.0f) UTEST_R2_FORM_WITH_RES_F(fsgnjn_s, float, 100.0f, 200.0f, -100.0f) UTEST_R2_FORM_WITH_RES_F(fsgnjx_s, float, -100.0f, 200.0f, -100.0f) // -- RV64F Standard Extension (in addition to RV32F) -- UTEST_LOAD_STORE_F(fld, fsd, double, -3456.678) UTEST_R2_FORM_WITH_OP_F(fadd_d, double, -1012.01, 3456.13, +) UTEST_R2_FORM_WITH_OP_F(fsub_d, double, -1012.01, 3456.13, -) UTEST_R2_FORM_WITH_OP_F(fmul_d, double, -10.01, 56.13, *) UTEST_R2_FORM_WITH_OP_F(fdiv_d, double, -10.01, 34.13, /) UTEST_R1_FORM_WITH_RES_F(fsqrt_d, double, 34.13, std::sqrt(34.13)) UTEST_R2_FORM_WITH_RES_F(fmin_d, double, -1012.0, 3456.13, -1012.0) UTEST_R2_FORM_WITH_RES_F(fmax_d, double, -1012.0, 3456.13, 3456.13) UTEST_R3_FORM_WITH_RES_F(fmadd_d, double, 67.56, -1012.01, 3456.13, std::fma(67.56, -1012.01, 3456.13)) UTEST_R3_FORM_WITH_RES_F(fmsub_d, double, 67.56, -1012.01, 3456.13, std::fma(67.56, -1012.01, -3456.13)) UTEST_R3_FORM_WITH_RES_F(fnmsub_d, double, 67.56, -1012.01, 3456.13, -std::fma(67.56, -1012.01, -3456.13)) UTEST_R3_FORM_WITH_RES_F(fnmadd_d, double, 67.56, -1012.01, 3456.13, -std::fma(67.56, -1012.01, 3456.13)) UTEST_COMPARE_WITH_OP_F(feq_d, double, -3456.56, -3456.56, ==) UTEST_COMPARE_WITH_OP_F(flt_d, double, -3456.56, -3456.56, <) UTEST_COMPARE_WITH_OP_F(fle_d, double, -3456.56, -3456.56, <=) UTEST_CONV_F_FROM_I(fcvt_d_w, int32_t, double, -100, -100.0) UTEST_CONV_F_FROM_I(fcvt_d_wu, uint32_t, double, std::numeric_limits::max(), (double)(std::numeric_limits::max())) UTEST_CONV_I_FROM_F(fcvt_w_d, double, int32_t, RTZ, -100.0, -100) UTEST_CONV_I_FROM_F(fcvt_wu_d, double, uint32_t, RTZ, (double)(std::numeric_limits::max()), std::numeric_limits::max()) // -- RV64F Standard Extension (in addition to RV32F) -- UTEST_CONV_I_FROM_F(fcvt_l_s, float, int64_t, RDN, -100.5f, -101) UTEST_CONV_I_FROM_F(fcvt_lu_s, float, uint64_t, RTZ, 1000001.0f, 1000001) UTEST_CONV_F_FROM_I(fcvt_s_l, int64_t, float, (-0x1234'5678'0000'0001LL), (float)(-0x1234'5678'0000'0001LL)) UTEST_CONV_F_FROM_I(fcvt_s_lu, uint64_t, float, std::numeric_limits::max(), (float)(std::numeric_limits::max())) // -- RV32D Standard Extension -- UTEST_CONV_F_FROM_F(fcvt_s_d, double, float, 100.0, 100.0f) UTEST_CONV_F_FROM_F(fcvt_d_s, float, double, 100.0f, 100.0) UTEST_R2_FORM_WITH_RES_F(fsgnj_d, double, -100.0, 200.0, 100.0) UTEST_R2_FORM_WITH_RES_F(fsgnjn_d, double, 100.0, 200.0, -100.0) UTEST_R2_FORM_WITH_RES_F(fsgnjx_d, double, -100.0, 200.0, -100.0) // -- RV64D Standard Extension (in addition to RV32D) -- UTEST_CONV_I_FROM_F(fcvt_l_d, double, int64_t, RNE, -100.5, -100) UTEST_CONV_I_FROM_F(fcvt_lu_d, double, uint64_t, RTZ, 2456.5, 2456) UTEST_CONV_F_FROM_I(fcvt_d_l, int64_t, double, (-0x1234'5678'0000'0001LL), (double)(-0x1234'5678'0000'0001LL)) UTEST_CONV_F_FROM_I(fcvt_d_lu, uint64_t, double, std::numeric_limits::max(), (double)(std::numeric_limits::max())) // -- RVZFA Standard Extension -- TEST_F(AssemblerRISCV64Test, RISCV_UTEST_fli_s) { if (!CpuFeatures::IsSupported(ZFA)) { return; } struct FliSTestCase { uint8_t imm5; float expected; }; FliSTestCase test_cases[] = { {0, -1.0f}, {1, 1.17549435e-38f}, {2, 1.52587890625e-5f}, {8, 0.25f}, {12, 0.5f}, {16, 1.0f}, {20, 2.0f}, {24, 8.0f}, {30, std::numeric_limits::infinity()}, }; for (auto& tc : test_cases) { auto fn = [imm5 = tc.imm5](MacroAssembler& assm) { __ fli_s(fa0, imm5); __ fmv_x_w(a0, fa0); }; auto res = GenAndRunTest(fn); float fres = base::bit_cast(static_cast(res)); if (tc.imm5 == 30) { CHECK(std::isinf(fres) && fres > 0); } else { CHECK_EQ(tc.expected, fres); } } } TEST_F(AssemblerRISCV64Test, RISCV_UTEST_fli_d) { if (!CpuFeatures::IsSupported(ZFA)) { return; } struct FliDTestCase { uint8_t imm5; double expected; }; FliDTestCase test_cases[] = { {0, -1.0}, {1, 2.2250738585072014e-308}, {2, 1.52587890625e-5}, {8, 0.25}, {12, 0.5}, {16, 1.0}, {20, 2.0}, {24, 8.0}, {30, std::numeric_limits::infinity()}, }; for (auto& tc : test_cases) { auto fn = [imm5 = tc.imm5](MacroAssembler& assm) { __ fli_d(fa0, imm5); __ fmv_x_d(a0, fa0); }; auto res = GenAndRunTest(fn); double dres = base::bit_cast(res); if (tc.imm5 == 30) { CHECK(std::isinf(dres) && dres > 0); } else { CHECK_EQ(tc.expected, dres); } } } TEST_F(AssemblerRISCV64Test, RISCV_UTEST_fround_s) { if (!CpuFeatures::IsSupported(ZFA)) { return; } struct FroundSTestCase { float input; float expected; FPURoundingMode rm; }; FroundSTestCase test_cases[] = { {1.5f, 2.0f, RNE}, {2.5f, 2.0f, RNE}, {-1.5f, -2.0f, RNE}, {1.5f, 1.0f, RTZ}, {-1.5f, -1.0f, RTZ}, {1.5f, 1.0f, RDN}, {-1.5f, -2.0f, RDN}, {1.5f, 2.0f, RUP}, {-1.5f, -1.0f, RUP}, {2.5f, 3.0f, RMM}, {-2.5f, -3.0f, RMM}, }; for (auto& tc : test_cases) { auto fn = [rm = tc.rm](MacroAssembler& assm) { __ fround_s(fa0, fa0, rm); }; auto res = GenAndRunTest(tc.input, fn); CHECK_EQ(tc.expected, res); } } TEST_F(AssemblerRISCV64Test, RISCV_UTEST_fround_d) { if (!CpuFeatures::IsSupported(ZFA)) { return; } struct FroundDTestCase { double input; double expected; FPURoundingMode rm; }; FroundDTestCase test_cases[] = { {1.5, 2.0, RNE}, {2.5, 2.0, RNE}, {-1.5, -2.0, RNE}, {1.5, 1.0, RTZ}, {-1.5, -1.0, RTZ}, {1.5, 1.0, RDN}, {-1.5, -2.0, RDN}, {1.5, 2.0, RUP}, {-1.5, -1.0, RUP}, {2.5, 3.0, RMM}, {-2.5, -3.0, RMM}, }; for (auto& tc : test_cases) { auto fn = [rm = tc.rm](MacroAssembler& assm) { __ fround_d(fa0, fa0, rm); }; auto res = GenAndRunTest(tc.input, fn); CHECK_EQ(tc.expected, res); } } TEST_F(AssemblerRISCV64Test, RISCV_UTEST_fcvtmod_w_d) { if (!CpuFeatures::IsSupported(ZFA)) { return; } auto FcvtmodHelper = [](uint64_t value_bits, int64_t expected) { auto fn = [](MacroAssembler& assm) { __ fcvtmod_w_d(a0, fa0); }; auto res = GenAndRunTest(base::bit_cast(value_bits), fn); CHECK_EQ(expected, res); }; // Simple values. FcvtmodHelper(0x0000000000000000ULL, 0); // 0.0 FcvtmodHelper(0x3ff0000000000000ULL, 1); // 1.0 FcvtmodHelper(0x3ff8000000000000ULL, 1); // 1.5 (rounds towards zero) FcvtmodHelper(0x4000000000000000ULL, 2); // 2.0 FcvtmodHelper(0x4024000000000000ULL, 10); // 10.0 // Negative values. FcvtmodHelper(0x8000000000000000ULL, 0); // -0.0 FcvtmodHelper(0xbff0000000000000ULL, -1); // -1.0 FcvtmodHelper(0xbff8000000000000ULL, -1); // -1.5 (rounds towards zero) FcvtmodHelper(0xc000000000000000ULL, -2); // -2.0 FcvtmodHelper(0xc024000000000000ULL, -10); // -10.0 // INT32_MAX and INT32_MIN. FcvtmodHelper(0x41dfffffffc00000ULL, 2147483647); // 2147483647.0 (INT32_MAX) FcvtmodHelper(0xc1e0000000000000ULL, -2147483648LL); // -2147483648.0 (INT32_MIN) // Values outside 32-bit range (mod 2^32). FcvtmodHelper(0x41e0000000000000ULL, -2147483648LL); // 2147483648.0 -> 0x80000000 FcvtmodHelper(0x41f0000000000000ULL, 0); // 4294967296.0 (2^32) -> 0 FcvtmodHelper(0x41F0000000100000ULL, 1); // 4294967297.0 -> 1 FcvtmodHelper(0xc1f0000000000000ULL, 0); // -4294967296.0 -> 0 FcvtmodHelper(0xC1F0000000100000ULL, -1); // -4294967297.0 -> -1 // Largest finite value (overflows to 0 mod 2^32). FcvtmodHelper(0x7fefffffffffffffULL, 0); FcvtmodHelper(0xffefffffffffffffULL, 0); // Infinity. FcvtmodHelper(0x7ff0000000000000ULL, 0); // +Inf FcvtmodHelper(0xfff0000000000000ULL, 0); // -Inf // NaNs. FcvtmodHelper(0x7ff8000000000000ULL, 0); // Canonical quiet NaN FcvtmodHelper(0x7ff923456789abcdULL, 0); // Quiet NaN FcvtmodHelper(0x7ff0000000000001ULL, 0); // Signalling NaN FcvtmodHelper(0x7ff123456789abcdULL, 0); // Signalling NaN FcvtmodHelper(0xfff8000000000000ULL, 0); // Negative quiet NaN FcvtmodHelper(0xfff923456789abcdULL, 0); // Negative quiet NaN // Subnormals. FcvtmodHelper(0x0000000000000001ULL, 0); // Smallest subnormal FcvtmodHelper(0x000fffffffffffffULL, 0); // Largest subnormal FcvtmodHelper(0x000123456789abcdULL, 0); // Subnormal FcvtmodHelper(0x8000000000000001ULL, 0); // Negative smallest subnormal FcvtmodHelper(0x800fffffffffffffULL, 0); // Negative largest subnormal // Small normal values. FcvtmodHelper(0x0010000000000000ULL, 0); // Smallest positive normal FcvtmodHelper(0x8010000000000000ULL, 0); // Negative smallest normal // Values near 0.5. FcvtmodHelper(0x3fe0000000000000ULL, 0); // 0.5 -> rounds to 0 FcvtmodHelper(0x3fdfffffffffffffULL, 0); // Just below 0.5 FcvtmodHelper(0x3fe0000000000001ULL, 0); // Just above 0.5 FcvtmodHelper(0xbfe0000000000000ULL, 0); // -0.5 -> rounds to 0 FcvtmodHelper(0xbfdfffffffffffffULL, 0); // Just below -0.5 FcvtmodHelper(0xbfe0000000000001ULL, 0); // Just above -0.5 // Values near 1.0. FcvtmodHelper(0x3fefffffffffffffULL, 0); // Just below 1.0 FcvtmodHelper(0x3ff0000000000001ULL, 1); // Just above 1.0 FcvtmodHelper(0xbfefffffffffffffULL, 0); // Just below -1.0 FcvtmodHelper(0xbff0000000000001ULL, -1); // Just above -1.0 } TEST_F(AssemblerRISCV64Test, RISCV_UTEST_fleq_s) { if (!CpuFeatures::IsSupported(ZFA)) { return; } auto FleqSHelper = [](float rs1, float rs2, int32_t expected) { auto fn = [](MacroAssembler& assm) { __ fleq_s(a0, fa0, fa1); }; auto res = GenAndRunTest(rs1, rs2, fn); CHECK_EQ(expected, res); }; // Normal comparisons FleqSHelper(1.0f, 2.0f, 1); // 1.0 <= 2.0 -> true FleqSHelper(2.0f, 1.0f, 0); // 2.0 <= 1.0 -> false FleqSHelper(1.0f, 1.0f, 1); // 1.0 <= 1.0 -> true FleqSHelper(-1.0f, 1.0f, 1); // -1.0 <= 1.0 -> true FleqSHelper(1.0f, -1.0f, 0); // 1.0 <= -1.0 -> false FleqSHelper(3.14f, 3.15f, 1); // 3.14 <= 3.15 -> true FleqSHelper(-100.0f, -50.0f, 1); // -100.0 <= -50.0 -> true // Zero comparisons FleqSHelper(0.0f, 0.0f, 1); // 0.0 <= 0.0 -> true FleqSHelper(base::bit_cast(0x80000000U), base::bit_cast(0x00000000U), 1); // -0.0 <= +0.0 FleqSHelper(base::bit_cast(0x00000000U), base::bit_cast(0x80000000U), 1); // +0.0 <= -0.0 FleqSHelper(base::bit_cast(0x80000000U), base::bit_cast(0x80000000U), 1); // -0.0 <= -0.0 FleqSHelper(0.0f, 1.0f, 1); // 0.0 <= 1.0 -> true FleqSHelper(-1.0f, 0.0f, 1); // -1.0 <= 0.0 -> true // NaN comparisons (should return 0, quiet - no exception) FleqSHelper(base::bit_cast(0x7fc00000U), base::bit_cast(0x3f800000U), 0); // NaN <= 1.0 FleqSHelper(base::bit_cast(0x3f800000U), base::bit_cast(0x7fc00000U), 0); // 1.0 <= NaN FleqSHelper(base::bit_cast(0x7fc00000U), base::bit_cast(0x7fc00000U), 0); // NaN <= NaN FleqSHelper(base::bit_cast(0x7ff00000U), base::bit_cast(0x3f800000U), 0); // Signaling NaN <= 1.0 FleqSHelper(base::bit_cast(0xffc00000U), base::bit_cast(0x3f800000U), 0); // -NaN <= 1.0 // Infinity comparisons FleqSHelper(base::bit_cast(0x7f800000U), base::bit_cast(0x3f800000U), 0); // +Inf <= 1.0 FleqSHelper(base::bit_cast(0x3f800000U), base::bit_cast(0x7f800000U), 1); // 1.0 <= +Inf FleqSHelper(base::bit_cast(0xff800000U), base::bit_cast(0x3f800000U), 1); // -Inf <= 1.0 FleqSHelper(base::bit_cast(0x7f800000U), base::bit_cast(0x7f800000U), 1); // +Inf <= +Inf FleqSHelper(base::bit_cast(0xff800000U), base::bit_cast(0xff800000U), 1); // -Inf <= -Inf FleqSHelper(base::bit_cast(0xff800000U), base::bit_cast(0x7f800000U), 1); // -Inf <= +Inf FleqSHelper(base::bit_cast(0x7f800000U), base::bit_cast(0xff800000U), 0); // +Inf <= -Inf // Denormal numbers FleqSHelper(base::bit_cast(0x00000001U), base::bit_cast(0x3f800000U), 1); // smallest denorm <= 1.0 FleqSHelper(base::bit_cast(0x3f800000U), base::bit_cast(0x00000001U), 0); // 1.0 <= smallest denorm FleqSHelper(base::bit_cast(0x007fffffU), base::bit_cast(0x00800000U), 1); // largest denorm <= smallest normal FleqSHelper(base::bit_cast(0x00000001U), base::bit_cast(0x00000002U), 1); // denorm 1 <= denorm 2 // Boundary values FleqSHelper(base::bit_cast(0x7f7fffffU), base::bit_cast(0x7f800000U), 1); // FLT_MAX <= +Inf FleqSHelper(base::bit_cast(0x7f800000U), base::bit_cast(0x7f7fffffU), 0); // +Inf <= FLT_MAX FleqSHelper(base::bit_cast(0x00800000U), base::bit_cast(0x00800001U), 1); // FLT_MIN <= FLT_MIN+1 } TEST_F(AssemblerRISCV64Test, RISCV_UTEST_fltq_s) { if (!CpuFeatures::IsSupported(ZFA)) { return; } auto FltqSHelper = [](float rs1, float rs2, int32_t expected) { auto fn = [](MacroAssembler& assm) { __ fltq_s(a0, fa0, fa1); }; auto res = GenAndRunTest(rs1, rs2, fn); CHECK_EQ(expected, res); }; // Normal comparisons FltqSHelper(1.0f, 2.0f, 1); // 1.0 < 2.0 -> true FltqSHelper(2.0f, 1.0f, 0); // 2.0 < 1.0 -> false FltqSHelper(1.0f, 1.0f, 0); // 1.0 < 1.0 -> false FltqSHelper(-1.0f, 1.0f, 1); // -1.0 < 1.0 -> true FltqSHelper(1.0f, -1.0f, 0); // 1.0 < -1.0 -> false FltqSHelper(3.14f, 3.15f, 1); // 3.14 < 3.15 -> true FltqSHelper(-100.0f, -50.0f, 1); // -100.0 < -50.0 -> true // Zero comparisons FltqSHelper(0.0f, 0.0f, 0); // 0.0 < 0.0 -> false FltqSHelper(base::bit_cast(0x80000000U), base::bit_cast(0x00000000U), 0); // -0.0 < +0.0 FltqSHelper(base::bit_cast(0x00000000U), base::bit_cast(0x80000000U), 0); // +0.0 < -0.0 FltqSHelper(base::bit_cast(0x80000000U), base::bit_cast(0x80000000U), 0); // -0.0 < -0.0 FltqSHelper(0.0f, 1.0f, 1); // 0.0 < 1.0 -> true FltqSHelper(-1.0f, 0.0f, 1); // -1.0 < 0.0 -> true // NaN comparisons (should return 0, quiet - no exception) FltqSHelper(base::bit_cast(0x7fc00000U), base::bit_cast(0x3f800000U), 0); // NaN < 1.0 FltqSHelper(base::bit_cast(0x3f800000U), base::bit_cast(0x7fc00000U), 0); // 1.0 < NaN FltqSHelper(base::bit_cast(0x7fc00000U), base::bit_cast(0x7fc00000U), 0); // NaN < NaN FltqSHelper(base::bit_cast(0x7ff00000U), base::bit_cast(0x3f800000U), 0); // Signaling NaN < 1.0 FltqSHelper(base::bit_cast(0xffc00000U), base::bit_cast(0x3f800000U), 0); // -NaN < 1.0 // Infinity comparisons FltqSHelper(base::bit_cast(0x7f800000U), base::bit_cast(0x3f800000U), 0); // +Inf < 1.0 FltqSHelper(base::bit_cast(0x3f800000U), base::bit_cast(0x7f800000U), 1); // 1.0 < +Inf FltqSHelper(base::bit_cast(0xff800000U), base::bit_cast(0x3f800000U), 1); // -Inf < 1.0 FltqSHelper(base::bit_cast(0x7f800000U), base::bit_cast(0x7f800000U), 0); // +Inf < +Inf FltqSHelper(base::bit_cast(0xff800000U), base::bit_cast(0xff800000U), 0); // -Inf < -Inf FltqSHelper(base::bit_cast(0xff800000U), base::bit_cast(0x7f800000U), 1); // -Inf < +Inf FltqSHelper(base::bit_cast(0x7f800000U), base::bit_cast(0xff800000U), 0); // +Inf < -Inf // Denormal numbers FltqSHelper(base::bit_cast(0x00000001U), base::bit_cast(0x3f800000U), 1); // smallest denorm < 1.0 FltqSHelper(base::bit_cast(0x3f800000U), base::bit_cast(0x00000001U), 0); // 1.0 < smallest denorm FltqSHelper(base::bit_cast(0x007fffffU), base::bit_cast(0x00800000U), 1); // largest denorm < smallest normal FltqSHelper(base::bit_cast(0x00000001U), base::bit_cast(0x00000002U), 1); // denorm 1 < denorm 2 // Boundary values FltqSHelper(base::bit_cast(0x7f7fffffU), base::bit_cast(0x7f800000U), 1); // FLT_MAX < +Inf FltqSHelper(base::bit_cast(0x7f800000U), base::bit_cast(0x7f7fffffU), 0); // +Inf < FLT_MAX FltqSHelper(base::bit_cast(0x00800000U), base::bit_cast(0x00800001U), 1); // FLT_MIN < FLT_MIN+1 } TEST_F(AssemblerRISCV64Test, RISCV_UTEST_fleq_d) { if (!CpuFeatures::IsSupported(ZFA)) { return; } auto FleqDHelper = [](double rs1, double rs2, int32_t expected) { auto fn = [](MacroAssembler& assm) { __ fleq_d(a0, fa0, fa1); }; auto res = GenAndRunTest(rs1, rs2, fn); CHECK_EQ(expected, res); }; // Normal comparisons FleqDHelper(1.0, 2.0, 1); // 1.0 <= 2.0 -> true FleqDHelper(2.0, 1.0, 0); // 2.0 <= 1.0 -> false FleqDHelper(1.0, 1.0, 1); // 1.0 <= 1.0 -> true FleqDHelper(-1.0, 1.0, 1); // -1.0 <= 1.0 -> true FleqDHelper(1.0, -1.0, 0); // 1.0 <= -1.0 -> false FleqDHelper(3.14159265358979, 3.1415926535898002, 1); // pi_small <= pi_large -> true FleqDHelper(-100.0, -50.0, 1); // -100.0 <= -50.0 -> true // Zero comparisons FleqDHelper(0.0, 0.0, 1); // 0.0 <= 0.0 -> true FleqDHelper(base::bit_cast(0x8000000000000000ULL), base::bit_cast(0x0000000000000000ULL), 1); // -0.0 <= +0.0 FleqDHelper(base::bit_cast(0x0000000000000000ULL), base::bit_cast(0x8000000000000000ULL), 1); // +0.0 <= -0.0 FleqDHelper(base::bit_cast(0x8000000000000000ULL), base::bit_cast(0x8000000000000000ULL), 1); // -0.0 <= -0.0 FleqDHelper(0.0, 1.0, 1); // 0.0 <= 1.0 -> true FleqDHelper(-1.0, 0.0, 1); // -1.0 <= 0.0 -> true // NaN comparisons (should return 0, quiet - no exception) FleqDHelper(base::bit_cast(0x7ff8000000000000ULL), base::bit_cast(0x3ff0000000000000ULL), 0); // NaN <= 1.0 FleqDHelper(base::bit_cast(0x3ff0000000000000ULL), base::bit_cast(0x7ff8000000000000ULL), 0); // 1.0 <= NaN FleqDHelper(base::bit_cast(0x7ff8000000000000ULL), base::bit_cast(0x7ff8000000000000ULL), 0); // NaN <= NaN FleqDHelper(base::bit_cast(0x7ff0000000000001ULL), base::bit_cast(0x3ff0000000000000ULL), 0); // Signaling NaN <= 1.0 FleqDHelper(base::bit_cast(0xfff8000000000000ULL), base::bit_cast(0x3ff0000000000000ULL), 0); // -NaN <= 1.0 // Infinity comparisons FleqDHelper(base::bit_cast(0x7ff0000000000000ULL), base::bit_cast(0x3ff0000000000000ULL), 0); // +Inf <= 1.0 FleqDHelper(base::bit_cast(0x3ff0000000000000ULL), base::bit_cast(0x7ff0000000000000ULL), 1); // 1.0 <= +Inf FleqDHelper(base::bit_cast(0xfff0000000000000ULL), base::bit_cast(0x3ff0000000000000ULL), 1); // -Inf <= 1.0 FleqDHelper(base::bit_cast(0x7ff0000000000000ULL), base::bit_cast(0x7ff0000000000000ULL), 1); // +Inf <= +Inf FleqDHelper(base::bit_cast(0xfff0000000000000ULL), base::bit_cast(0xfff0000000000000ULL), 1); // -Inf <= -Inf FleqDHelper(base::bit_cast(0xfff0000000000000ULL), base::bit_cast(0x7ff0000000000000ULL), 1); // -Inf <= +Inf FleqDHelper(base::bit_cast(0x7ff0000000000000ULL), base::bit_cast(0xfff0000000000000ULL), 0); // +Inf <= -Inf // Denormal numbers FleqDHelper(base::bit_cast(0x0000000000000001ULL), base::bit_cast(0x3ff0000000000000ULL), 1); // smallest denorm <= 1.0 FleqDHelper(base::bit_cast(0x3ff0000000000000ULL), base::bit_cast(0x0000000000000001ULL), 0); // 1.0 <= smallest denorm FleqDHelper(base::bit_cast(0x000fffffffffffffULL), base::bit_cast(0x0010000000000000ULL), 1); // largest denorm <= smallest normal FleqDHelper(base::bit_cast(0x0000000000000001ULL), base::bit_cast(0x0000000000000002ULL), 1); // denorm 1 <= denorm 2 // Boundary values FleqDHelper(base::bit_cast(0x7fefffffffffffffULL), base::bit_cast(0x7ff0000000000000ULL), 1); // DBL_MAX <= +Inf FleqDHelper(base::bit_cast(0x7ff0000000000000ULL), base::bit_cast(0x7fefffffffffffffULL), 0); // +Inf <= DBL_MAX FleqDHelper(base::bit_cast(0x0010000000000000ULL), base::bit_cast(0x0010000000000001ULL), 1); // DBL_MIN <= DBL_MIN+1 // Large integer range values FleqDHelper(2147483647.0, 2147483648.0, 1); // INT32_MAX <= INT32_MAX+1 FleqDHelper(-2147483648.0, 0.0, 1); // INT32_MIN <= 0.0 FleqDHelper(9007199254740992.0, 9007199254740992.0, 1); // 2^53 <= 2^53 } TEST_F(AssemblerRISCV64Test, RISCV_UTEST_fltq_d) { if (!CpuFeatures::IsSupported(ZFA)) { return; } auto FltqDHelper = [](double rs1, double rs2, int32_t expected) { auto fn = [](MacroAssembler& assm) { __ fltq_d(a0, fa0, fa1); }; auto res = GenAndRunTest(rs1, rs2, fn); CHECK_EQ(expected, res); }; // Normal comparisons FltqDHelper(1.0, 2.0, 1); // 1.0 < 2.0 -> true FltqDHelper(2.0, 1.0, 0); // 2.0 < 1.0 -> false FltqDHelper(1.0, 1.0, 0); // 1.0 < 1.0 -> false FltqDHelper(-1.0, 1.0, 1); // -1.0 < 1.0 -> true FltqDHelper(1.0, -1.0, 0); // 1.0 < -1.0 -> false FltqDHelper(3.14159265358979, 3.1415926535898002, 1); // pi_small < pi_large -> true FltqDHelper(-100.0, -50.0, 1); // -100.0 < -50.0 -> true // Zero comparisons FltqDHelper(0.0, 0.0, 0); // 0.0 < 0.0 -> false FltqDHelper(base::bit_cast(0x8000000000000000ULL), base::bit_cast(0x0000000000000000ULL), 0); // -0.0 < +0.0 FltqDHelper(base::bit_cast(0x0000000000000000ULL), base::bit_cast(0x8000000000000000ULL), 0); // +0.0 < -0.0 FltqDHelper(base::bit_cast(0x8000000000000000ULL), base::bit_cast(0x8000000000000000ULL), 0); // -0.0 < -0.0 FltqDHelper(0.0, 1.0, 1); // 0.0 < 1.0 -> true FltqDHelper(-1.0, 0.0, 1); // -1.0 < 0.0 -> true // NaN comparisons (should return 0, quiet - no exception) FltqDHelper(base::bit_cast(0x7ff8000000000000ULL), base::bit_cast(0x3ff0000000000000ULL), 0); // NaN < 1.0 FltqDHelper(base::bit_cast(0x3ff0000000000000ULL), base::bit_cast(0x7ff8000000000000ULL), 0); // 1.0 < NaN FltqDHelper(base::bit_cast(0x7ff8000000000000ULL), base::bit_cast(0x7ff8000000000000ULL), 0); // NaN < NaN FltqDHelper(base::bit_cast(0x7ff0000000000001ULL), base::bit_cast(0x3ff0000000000000ULL), 0); // Signaling NaN < 1.0 FltqDHelper(base::bit_cast(0xfff8000000000000ULL), base::bit_cast(0x3ff0000000000000ULL), 0); // -NaN < 1.0 // Infinity comparisons FltqDHelper(base::bit_cast(0x7ff0000000000000ULL), base::bit_cast(0x3ff0000000000000ULL), 0); // +Inf < 1.0 FltqDHelper(base::bit_cast(0x3ff0000000000000ULL), base::bit_cast(0x7ff0000000000000ULL), 1); // 1.0 < +Inf FltqDHelper(base::bit_cast(0xfff0000000000000ULL), base::bit_cast(0x3ff0000000000000ULL), 1); // -Inf < 1.0 FltqDHelper(base::bit_cast(0x7ff0000000000000ULL), base::bit_cast(0x7ff0000000000000ULL), 0); // +Inf < +Inf FltqDHelper(base::bit_cast(0xfff0000000000000ULL), base::bit_cast(0xfff0000000000000ULL), 0); // -Inf < -Inf FltqDHelper(base::bit_cast(0xfff0000000000000ULL), base::bit_cast(0x7ff0000000000000ULL), 1); // -Inf < +Inf FltqDHelper(base::bit_cast(0x7ff0000000000000ULL), base::bit_cast(0xfff0000000000000ULL), 0); // +Inf < -Inf // Denormal numbers FltqDHelper(base::bit_cast(0x0000000000000001ULL), base::bit_cast(0x3ff0000000000000ULL), 1); // smallest denorm < 1.0 FltqDHelper(base::bit_cast(0x3ff0000000000000ULL), base::bit_cast(0x0000000000000001ULL), 0); // 1.0 < smallest denorm FltqDHelper(base::bit_cast(0x000fffffffffffffULL), base::bit_cast(0x0010000000000000ULL), 1); // largest denorm < smallest normal FltqDHelper(base::bit_cast(0x0000000000000001ULL), base::bit_cast(0x0000000000000002ULL), 1); // denorm 1 < denorm 2 // Boundary values FltqDHelper(base::bit_cast(0x7fefffffffffffffULL), base::bit_cast(0x7ff0000000000000ULL), 1); // DBL_MAX < +Inf FltqDHelper(base::bit_cast(0x7ff0000000000000ULL), base::bit_cast(0x7fefffffffffffffULL), 0); // +Inf < DBL_MAX FltqDHelper(base::bit_cast(0x0010000000000000ULL), base::bit_cast(0x0010000000000001ULL), 1); // DBL_MIN < DBL_MIN+1 // Large integer range values FltqDHelper(2147483647.0, 2147483648.0, 1); // INT32_MAX < INT32_MAX+1 FltqDHelper(-2147483648.0, 0.0, 1); // INT32_MIN < 0.0 FltqDHelper(9007199254740992.0, 9007199254740992.0, 0); // 2^53 < 2^53 } TEST_F(AssemblerRISCV64Test, RISCV_UTEST_fminm_s) { if (!CpuFeatures::IsSupported(ZFA)) { return; } auto FminmSHelper = [](float rs1, float rs2, uint32_t expected_bits) { auto fn = [](MacroAssembler& assm) { __ fminm_s(fa0, fa0, fa1); }; auto res = GenAndRunTest(rs1, rs2, fn); CHECK_EQ(expected_bits, base::bit_cast(res)); }; // Normal comparisons FminmSHelper(1.0f, 2.0f, 0x3f800000U); FminmSHelper(2.0f, 1.0f, 0x3f800000U); FminmSHelper(-1.0f, 1.0f, 0xbf800000U); FminmSHelper(1.0f, -1.0f, 0xbf800000U); FminmSHelper(3.14f, 3.15f, 0x4048f5c3U); FminmSHelper(-100.0f, -50.0f, 0xc2c80000U); // Zero comparisons FminmSHelper(0.0f, 0.0f, 0x00000000U); FminmSHelper(base::bit_cast(0x80000000U), base::bit_cast(0x00000000U), 0x80000000U); // min(-0.0, +0.0) = -0.0 FminmSHelper(base::bit_cast(0x00000000U), base::bit_cast(0x80000000U), 0x80000000U); // min(+0.0, -0.0) = -0.0 FminmSHelper(0.0f, 1.0f, 0x00000000U); FminmSHelper(-1.0f, 0.0f, 0xbf800000U); // NaN handling (IEEE 754-2019: returns canonical qNaN) FminmSHelper(base::bit_cast(0x7fc00000U), base::bit_cast(0x3f800000U), 0x7fc00000U); // min(qNaN, 1.0) = qNaN FminmSHelper(base::bit_cast(0x3f800000U), base::bit_cast(0x7fc00000U), 0x7fc00000U); // min(1.0, qNaN) = qNaN FminmSHelper(base::bit_cast(0x7fc00000U), base::bit_cast(0x7fc00000U), 0x7fc00000U); // min(qNaN, qNaN) = qNaN FminmSHelper(base::bit_cast(0x7ff00000U), base::bit_cast(0x3f800000U), 0x7fc00000U); // min(sNaN, 1.0) = canonical qNaN FminmSHelper(base::bit_cast(0xffc00000U), base::bit_cast(0x3f800000U), 0x7fc00000U); // min(-qNaN, 1.0) = canonical qNaN // Infinity comparisons FminmSHelper(base::bit_cast(0x7f800000U), base::bit_cast(0x3f800000U), 0x3f800000U); // min(+Inf, 1.0) = 1.0 FminmSHelper(base::bit_cast(0x3f800000U), base::bit_cast(0x7f800000U), 0x3f800000U); // min(1.0, +Inf) = 1.0 FminmSHelper(base::bit_cast(0xff800000U), base::bit_cast(0x3f800000U), 0xff800000U); // min(-Inf, 1.0) = -Inf FminmSHelper(base::bit_cast(0x7f800000U), base::bit_cast(0xff800000U), 0xff800000U); // min(+Inf, -Inf) = -Inf FminmSHelper(base::bit_cast(0x7f800000U), base::bit_cast(0x7f800000U), 0x7f800000U); // min(+Inf, +Inf) = +Inf FminmSHelper(base::bit_cast(0xff800000U), base::bit_cast(0xff800000U), 0xff800000U); // min(-Inf, -Inf) = -Inf // Denormal numbers FminmSHelper(base::bit_cast(0x00000001U), base::bit_cast(0x3f800000U), 0x00000001U); // min(smallest denorm, 1.0) FminmSHelper(base::bit_cast(0x3f800000U), base::bit_cast(0x00000001U), 0x00000001U); // min(1.0, smallest denorm) FminmSHelper(base::bit_cast(0x007fffffU), base::bit_cast(0x00800000U), 0x007fffffU); // min(largest denorm, smallest normal) FminmSHelper(base::bit_cast(0x00000001U), base::bit_cast(0x00000002U), 0x00000001U); // min(denorm1, denorm2) // Boundary values FminmSHelper(base::bit_cast(0x7f7fffffU), base::bit_cast(0x7f800000U), 0x7f7fffffU); // min(FLT_MAX, +Inf) FminmSHelper(base::bit_cast(0x00800000U), base::bit_cast(0x00800001U), 0x00800000U); // min(FLT_MIN, FLT_MIN+1) } TEST_F(AssemblerRISCV64Test, RISCV_UTEST_fminm_d) { if (!CpuFeatures::IsSupported(ZFA)) { return; } auto FminmDHelper = [](double rs1, double rs2, uint64_t expected_bits) { auto fn = [](MacroAssembler& assm) { __ fminm_d(fa0, fa0, fa1); }; auto res = GenAndRunTest(rs1, rs2, fn); CHECK_EQ(expected_bits, base::bit_cast(res)); }; // Normal comparisons FminmDHelper(1.0, 2.0, 0x3ff0000000000000ULL); FminmDHelper(2.0, 1.0, 0x3ff0000000000000ULL); FminmDHelper(-1.0, 1.0, 0xbff0000000000000ULL); FminmDHelper(1.0, -1.0, 0xbff0000000000000ULL); // Zero comparisons FminmDHelper(0.0, 0.0, 0x0000000000000000ULL); FminmDHelper(base::bit_cast(0x8000000000000000ULL), base::bit_cast(0x0000000000000000ULL), 0x8000000000000000ULL); // min(-0.0, +0.0) = -0.0 FminmDHelper(base::bit_cast(0x0000000000000000ULL), base::bit_cast(0x8000000000000000ULL), 0x8000000000000000ULL); // min(+0.0, -0.0) = -0.0 // NaN handling (returns canonical qNaN) FminmDHelper(base::bit_cast(0x7ff8000000000000ULL), base::bit_cast(0x3ff0000000000000ULL), 0x7ff8000000000000ULL); // min(qNaN, 1.0) = qNaN FminmDHelper(base::bit_cast(0x3ff0000000000000ULL), base::bit_cast(0x7ff8000000000000ULL), 0x7ff8000000000000ULL); // min(1.0, qNaN) = qNaN FminmDHelper(base::bit_cast(0x7ff8000000000000ULL), base::bit_cast(0x7ff8000000000000ULL), 0x7ff8000000000000ULL); // min(qNaN, qNaN) = qNaN FminmDHelper(base::bit_cast(0x7ff0000000000001ULL), base::bit_cast(0x3ff0000000000000ULL), 0x7ff8000000000000ULL); // min(sNaN, 1.0) = canonical qNaN FminmDHelper(base::bit_cast(0xfff8000000000000ULL), base::bit_cast(0x3ff0000000000000ULL), 0x7ff8000000000000ULL); // min(-qNaN, 1.0) = canonical qNaN // Infinity comparisons FminmDHelper(base::bit_cast(0x7ff0000000000000ULL), base::bit_cast(0x3ff0000000000000ULL), 0x3ff0000000000000ULL); // min(+Inf, 1.0) = 1.0 FminmDHelper(base::bit_cast(0xfff0000000000000ULL), base::bit_cast(0x3ff0000000000000ULL), 0xfff0000000000000ULL); // min(-Inf, 1.0) = -Inf FminmDHelper(base::bit_cast(0x7ff0000000000000ULL), base::bit_cast(0xfff0000000000000ULL), 0xfff0000000000000ULL); // min(+Inf, -Inf) = -Inf // Denormal numbers FminmDHelper(base::bit_cast(0x0000000000000001ULL), base::bit_cast(0x3ff0000000000000ULL), 0x0000000000000001ULL); // min(smallest denorm, 1.0) FminmDHelper(base::bit_cast(0x000fffffffffffffULL), base::bit_cast(0x0010000000000000ULL), 0x000fffffffffffffULL); // min(largest denorm, smallest normal) } TEST_F(AssemblerRISCV64Test, RISCV_UTEST_fmaxm_s) { if (!CpuFeatures::IsSupported(ZFA)) { return; } auto FmaxmSHelper = [](float rs1, float rs2, uint32_t expected_bits) { auto fn = [](MacroAssembler& assm) { __ fmaxm_s(fa0, fa0, fa1); }; auto res = GenAndRunTest(rs1, rs2, fn); CHECK_EQ(expected_bits, base::bit_cast(res)); }; // Normal comparisons FmaxmSHelper(1.0f, 2.0f, 0x40000000U); FmaxmSHelper(2.0f, 1.0f, 0x40000000U); FmaxmSHelper(-1.0f, 1.0f, 0x3f800000U); FmaxmSHelper(1.0f, -1.0f, 0x3f800000U); // Zero comparisons FmaxmSHelper(0.0f, 0.0f, 0x00000000U); FmaxmSHelper(base::bit_cast(0x80000000U), base::bit_cast(0x00000000U), 0x00000000U); // max(-0.0, +0.0) = +0.0 FmaxmSHelper(base::bit_cast(0x00000000U), base::bit_cast(0x80000000U), 0x00000000U); // max(+0.0, -0.0) = +0.0 // NaN handling (returns canonical qNaN) FmaxmSHelper(base::bit_cast(0x7fc00000U), base::bit_cast(0x3f800000U), 0x7fc00000U); // max(qNaN, 1.0) = qNaN FmaxmSHelper(base::bit_cast(0x3f800000U), base::bit_cast(0x7fc00000U), 0x7fc00000U); // max(1.0, qNaN) = qNaN FmaxmSHelper(base::bit_cast(0x7fc00000U), base::bit_cast(0x7fc00000U), 0x7fc00000U); // max(qNaN, qNaN) = qNaN FmaxmSHelper(base::bit_cast(0x7ff00000U), base::bit_cast(0x3f800000U), 0x7fc00000U); // max(sNaN, 1.0) = canonical qNaN FmaxmSHelper(base::bit_cast(0xffc00000U), base::bit_cast(0x3f800000U), 0x7fc00000U); // max(-qNaN, 1.0) = canonical qNaN // Infinity comparisons FmaxmSHelper(base::bit_cast(0x7f800000U), base::bit_cast(0x3f800000U), 0x7f800000U); // max(+Inf, 1.0) = +Inf FmaxmSHelper(base::bit_cast(0xff800000U), base::bit_cast(0x3f800000U), 0x3f800000U); // max(-Inf, 1.0) = 1.0 FmaxmSHelper(base::bit_cast(0x7f800000U), base::bit_cast(0xff800000U), 0x7f800000U); // max(+Inf, -Inf) = +Inf // Denormal numbers FmaxmSHelper(base::bit_cast(0x00000001U), base::bit_cast(0x3f800000U), 0x3f800000U); // max(smallest denorm, 1.0) FmaxmSHelper(base::bit_cast(0x007fffffU), base::bit_cast(0x00800000U), 0x00800000U); // max(largest denorm, smallest normal) } TEST_F(AssemblerRISCV64Test, RISCV_UTEST_fmaxm_d) { if (!CpuFeatures::IsSupported(ZFA)) { return; } auto FmaxmDHelper = [](double rs1, double rs2, uint64_t expected_bits) { auto fn = [](MacroAssembler& assm) { __ fmaxm_d(fa0, fa0, fa1); }; auto res = GenAndRunTest(rs1, rs2, fn); CHECK_EQ(expected_bits, base::bit_cast(res)); }; // Normal comparisons FmaxmDHelper(1.0, 2.0, 0x4000000000000000ULL); FmaxmDHelper(2.0, 1.0, 0x4000000000000000ULL); FmaxmDHelper(-1.0, 1.0, 0x3ff0000000000000ULL); FmaxmDHelper(1.0, -1.0, 0x3ff0000000000000ULL); // Zero comparisons FmaxmDHelper(0.0, 0.0, 0x0000000000000000ULL); FmaxmDHelper(base::bit_cast(0x8000000000000000ULL), base::bit_cast(0x0000000000000000ULL), 0x0000000000000000ULL); // max(-0.0, +0.0) = +0.0 FmaxmDHelper(base::bit_cast(0x0000000000000000ULL), base::bit_cast(0x8000000000000000ULL), 0x0000000000000000ULL); // max(+0.0, -0.0) = +0.0 // NaN handling (returns canonical qNaN) FmaxmDHelper(base::bit_cast(0x7ff8000000000000ULL), base::bit_cast(0x3ff0000000000000ULL), 0x7ff8000000000000ULL); // max(qNaN, 1.0) = qNaN FmaxmDHelper(base::bit_cast(0x3ff0000000000000ULL), base::bit_cast(0x7ff8000000000000ULL), 0x7ff8000000000000ULL); // max(1.0, qNaN) = qNaN FmaxmDHelper(base::bit_cast(0x7ff8000000000000ULL), base::bit_cast(0x7ff8000000000000ULL), 0x7ff8000000000000ULL); // max(qNaN, qNaN) = qNaN FmaxmDHelper(base::bit_cast(0x7ff0000000000001ULL), base::bit_cast(0x3ff0000000000000ULL), 0x7ff8000000000000ULL); // max(sNaN, 1.0) = canonical qNaN FmaxmDHelper(base::bit_cast(0xfff8000000000000ULL), base::bit_cast(0x3ff0000000000000ULL), 0x7ff8000000000000ULL); // max(-qNaN, 1.0) = canonical qNaN // Infinity comparisons FmaxmDHelper(base::bit_cast(0x7ff0000000000000ULL), base::bit_cast(0x3ff0000000000000ULL), 0x7ff0000000000000ULL); // max(+Inf, 1.0) = +Inf FmaxmDHelper(base::bit_cast(0xfff0000000000000ULL), base::bit_cast(0x3ff0000000000000ULL), 0x3ff0000000000000ULL); // max(-Inf, 1.0) = 1.0 FmaxmDHelper(base::bit_cast(0x7ff0000000000000ULL), base::bit_cast(0xfff0000000000000ULL), 0x7ff0000000000000ULL); // max(+Inf, -Inf) = +Inf // Denormal numbers FmaxmDHelper(base::bit_cast(0x0000000000000001ULL), base::bit_cast(0x3ff0000000000000ULL), 0x3ff0000000000000ULL); // max(smallest denorm, 1.0) FmaxmDHelper(base::bit_cast(0x000fffffffffffffULL), base::bit_cast(0x0010000000000000ULL), 0x0010000000000000ULL); // max(largest denorm, smallest normal) } TEST_F(AssemblerRISCV64Test, RISCV_UTEST_froundnx_s) { if (!CpuFeatures::IsSupported(ZFA)) { return; } auto FroundnxSHelper = [](float rs1, uint32_t expected_bits) { auto fn = [](MacroAssembler& assm) { __ froundnx_s(fa0, fa0); }; auto res = GenAndRunTest(rs1, fn); CHECK_EQ(expected_bits, base::bit_cast(res)); }; // Normal values FroundnxSHelper(1.0f, 0x3f800000U); FroundnxSHelper(2.0f, 0x40000000U); FroundnxSHelper(0.5f, 0x00000000U); // 0.5 rounds to 0 (RNE) FroundnxSHelper(-1.0f, 0xbf800000U); // Round to nearest (ties to even) FroundnxSHelper(1.5f, 0x40000000U); // 1.5 -> 2.0 FroundnxSHelper(2.0f, 0x40000000U); // 2.0 -> 2.0 FroundnxSHelper(3.0f, 0x40400000U); // 3.0 -> 3.0 FroundnxSHelper(3.5f, 0x40800000U); // 3.5 -> 4.0 FroundnxSHelper(4.0f, 0x40800000U); // 4.0 -> 4.0 FroundnxSHelper(5.0f, 0x40a00000U); // 5.0 -> 5.0 FroundnxSHelper(6.0f, 0x40c00000U); // 6.0 -> 6.0 FroundnxSHelper(7.0f, 0x40e00000U); // 7.0 -> 7.0 FroundnxSHelper(8.0f, 0x41000000U); // 8.0 -> 8.0 // Negative values FroundnxSHelper(-1.5f, 0xc0000000U); // -1.5 -> -2.0 FroundnxSHelper(-3.5f, 0xc0800000U); // -3.5 -> -4.0 // Zero FroundnxSHelper(0.0f, 0x00000000U); FroundnxSHelper(base::bit_cast(0x80000000U), 0x80000000U); // -0.0 // NaN (returns canonical qNaN) FroundnxSHelper(base::bit_cast(0x7fc00000U), 0x7fc00000U); // qNaN FroundnxSHelper(base::bit_cast(0x7ff00000U), 0x7fc00000U); // sNaN -> canonical qNaN FroundnxSHelper(base::bit_cast(0xffc00000U), 0x7fc00000U); // -qNaN -> canonical qNaN // Infinity FroundnxSHelper(base::bit_cast(0x7f800000U), 0x7f800000U); // +Inf FroundnxSHelper(base::bit_cast(0xff800000U), 0xff800000U); // -Inf // Denormal numbers (round to zero) FroundnxSHelper(base::bit_cast(0x00000001U), 0x00000000U); // smallest denorm FroundnxSHelper(base::bit_cast(0x007fffffU), 0x00000000U); // largest denorm } TEST_F(AssemblerRISCV64Test, RISCV_UTEST_froundnx_d) { if (!CpuFeatures::IsSupported(ZFA)) { return; } auto FroundnxDHelper = [](double rs1, uint64_t expected_bits) { auto fn = [](MacroAssembler& assm) { __ froundnx_d(fa0, fa0); }; auto res = GenAndRunTest(rs1, fn); CHECK_EQ(expected_bits, base::bit_cast(res)); }; // Normal values FroundnxDHelper(1.0, 0x3ff0000000000000ULL); FroundnxDHelper(2.0, 0x4000000000000000ULL); FroundnxDHelper(0.5, 0x0000000000000000ULL); // 0.5 rounds to 0 (RNE) FroundnxDHelper(-1.0, 0xbff0000000000000ULL); // Round to nearest (ties to even) FroundnxDHelper(1.5, 0x4000000000000000ULL); // 1.5 -> 2.0 FroundnxDHelper(2.0, 0x4000000000000000ULL); // 2.0 -> 2.0 FroundnxDHelper(3.0, 0x4008000000000000ULL); // 3.0 -> 3.0 FroundnxDHelper(3.5, 0x4010000000000000ULL); // 3.5 -> 4.0 FroundnxDHelper(4.0, 0x4010000000000000ULL); // 4.0 -> 4.0 FroundnxDHelper(5.0, 0x4014000000000000ULL); // 5.0 -> 5.0 FroundnxDHelper(6.0, 0x4018000000000000ULL); // 6.0 -> 6.0 FroundnxDHelper(7.0, 0x401c000000000000ULL); // 7.0 -> 7.0 FroundnxDHelper(8.0, 0x4020000000000000ULL); // 8.0 -> 8.0 // Negative values FroundnxDHelper(-1.5, 0xc000000000000000ULL); // -1.5 -> -2.0 FroundnxDHelper(-3.5, 0xc010000000000000ULL); // -3.5 -> -4.0 // Zero FroundnxDHelper(0.0, 0x0000000000000000ULL); FroundnxDHelper(base::bit_cast(0x8000000000000000ULL), 0x8000000000000000ULL); // -0.0 // NaN (returns canonical qNaN) FroundnxDHelper(base::bit_cast(0x7ff8000000000000ULL), 0x7ff8000000000000ULL); // qNaN FroundnxDHelper(base::bit_cast(0x7ff0000000000001ULL), 0x7ff8000000000000ULL); // sNaN -> canonical qNaN FroundnxDHelper(base::bit_cast(0xfff8000000000000ULL), 0x7ff8000000000000ULL); // -qNaN -> canonical qNaN // Infinity FroundnxDHelper(base::bit_cast(0x7ff0000000000000ULL), 0x7ff0000000000000ULL); // +Inf FroundnxDHelper(base::bit_cast(0xfff0000000000000ULL), 0xfff0000000000000ULL); // -Inf // Denormal numbers (round to zero) FroundnxDHelper(base::bit_cast(0x0000000000000001ULL), 0x0000000000000000ULL); // smallest denorm FroundnxDHelper(base::bit_cast(0x000fffffffffffffULL), 0x0000000000000000ULL); // largest denorm } // --RVZFH Standard Extension -- TEST_F(AssemblerRISCV64Test, RISCV_UTEST_flh_fsh) { if (!CpuFeatures::IsSupported(ZFH)) { return; } auto fn = [](MacroAssembler& assm) { __ fsh(fa0, a0, 0); __ flh(fa0, a0, 0); }; GenAndRunTestForLoadStore( Float16::FromFloat32(-2345.678f).get_bits(), fn); } const std::vector> fp16_test_values() { std::pair kValues[] = { std::make_pair(2.980232238769532e-8, DoubleToFloat16(5.960464477539063e-8f)), std::make_pair(1.1, DoubleToFloat16(1.1)), std::make_pair(0.00006103515625, DoubleToFloat16(0.00006103515625)), std::make_pair(static_cast(2051), DoubleToFloat16(2051.0))}; return std::vector>(&kValues[0], &kValues[arraysize(kValues)]); } TEST_F(AssemblerRISCV64Test, RISCV_UTEST_fcvthd) { if (!CpuFeatures::IsSupported(ZFH)) { return; } auto value = fp16_test_values(); for (auto i = value.begin(); i != value.end(); ++i) { auto fn = [](MacroAssembler& assm) { __ fcvt_h_d(fa1, fa0); __ fmv_x_h(a0, fa1); }; auto res = GenAndRunTest(i->first, fn); CHECK_EQ(i->second, res); } } namespace { struct H { static uint16_t bits(float f) { return Float16::FromFloat32(f).get_bits(); } }; template uint16_t RunHalfUnary(uint16_t input, F&& op) { auto fn = [&op](MacroAssembler& assm) { __ fmv_h_x(fa0, a0); op(assm); __ fmv_x_h(a0, fa0); }; return static_cast( GenAndRunTest(static_cast(input), fn)); } template uint16_t RunHalfBinary(uint16_t a, uint16_t b, F&& op) { auto fn = [&op](MacroAssembler& assm) { __ fmv_h_x(fa0, a0); __ fmv_h_x(fa1, a1); op(assm); __ fmv_x_h(a0, fa0); }; return static_cast(GenAndRunTest( static_cast(a), static_cast(b), fn)); } template uint16_t RunHalfTernary(uint16_t a, uint16_t b, uint16_t c, F&& op) { auto fn = [&op](MacroAssembler& assm) { __ fmv_h_x(fa0, a0); __ fmv_h_x(fa1, a1); __ fmv_h_x(fa2, a2); op(assm); __ fmv_x_h(a0, fa0); }; return static_cast(GenAndRunTest( static_cast(a), static_cast(b), static_cast(c), fn)); } template int32_t RunHalfCompare(uint16_t a, uint16_t b, F&& op) { auto fn = [&op](MacroAssembler& assm) { __ fmv_h_x(fa0, a0); __ fmv_h_x(fa1, a1); op(assm); }; return GenAndRunTest(static_cast(a), static_cast(b), fn); } constexpr uint16_t kFP16NegZero = 0x8000u; constexpr uint16_t kFP16NegInfinity = 0xFC00u; } // namespace TEST_F(AssemblerRISCV64Test, RISCV_UTEST_fadd_h) { if (!CpuFeatures::IsSupported(ZFH)) return; auto op = [](MacroAssembler& assm) { __ fadd_h(fa0, fa0, fa1); }; FOR_FLOAT32_INPUTS(i) { FOR_FLOAT32_INPUTS(j) { Float16 hi = Float16::FromFloat32(i); Float16 hj = Float16::FromFloat32(j); float sum = hi.ToFloat32() + hj.ToFloat32(); if (std::isnan(sum)) sum = std::numeric_limits::quiet_NaN(); uint16_t expected = Float16::FromFloat32(sum).get_bits(); CHECK_EQ(expected, RunHalfBinary(hi.get_bits(), hj.get_bits(), op)); } } } TEST_F(AssemblerRISCV64Test, RISCV_UTEST_fsub_h) { if (!CpuFeatures::IsSupported(ZFH)) return; auto op = [](MacroAssembler& assm) { __ fsub_h(fa0, fa0, fa1); }; auto check = [&op](float a, float b) { Float16 ha = Float16::FromFloat32(a); Float16 hb = Float16::FromFloat32(b); float result = ha.ToFloat32() - hb.ToFloat32(); if (std::isnan(result)) result = std::numeric_limits::quiet_NaN(); uint16_t expected = Float16::FromFloat32(result).get_bits(); CHECK_EQ(expected, RunHalfBinary(ha.get_bits(), hb.get_bits(), op)); }; check(3.0f, 2.0f); check(0.1f, 1.0f); check(1.0f, 1.0f); } TEST_F(AssemblerRISCV64Test, RISCV_UTEST_fmul_h) { if (!CpuFeatures::IsSupported(ZFH)) return; auto op = [](MacroAssembler& assm) { __ fmul_h(fa0, fa0, fa1); }; auto check = [&op](float a, float b) { Float16 ha = Float16::FromFloat32(a); Float16 hb = Float16::FromFloat32(b); float result = ha.ToFloat32() * hb.ToFloat32(); if (std::isnan(result)) result = std::numeric_limits::quiet_NaN(); uint16_t expected = Float16::FromFloat32(result).get_bits(); CHECK_EQ(expected, RunHalfBinary(ha.get_bits(), hb.get_bits(), op)); }; check(2.2f, 3.7f); check(1.4f, -2.13f); check(0.07f, 5.12f); } TEST_F(AssemblerRISCV64Test, RISCV_UTEST_fdiv_h) { if (!CpuFeatures::IsSupported(ZFH)) return; auto op = [](MacroAssembler& assm) { __ fdiv_h(fa0, fa0, fa1); }; auto check = [&op](float a, float b) { Float16 ha = Float16::FromFloat32(a); Float16 hb = Float16::FromFloat32(b); float result = ha.ToFloat32() / hb.ToFloat32(); if (std::isnan(result)) result = std::numeric_limits::quiet_NaN(); uint16_t expected = Float16::FromFloat32(result).get_bits(); CHECK_EQ(expected, RunHalfBinary(ha.get_bits(), hb.get_bits(), op)); }; check(3.0f, 2.0f); check(4.0f, -2.0f); check(1.0f, 0.0f); } TEST_F(AssemblerRISCV64Test, RISCV_UTEST_fsqrt_h) { if (!CpuFeatures::IsSupported(ZFH)) return; auto op = [](MacroAssembler& assm) { __ fsqrt_h(fa0, fa0); }; CHECK_EQ(H::bits(2.0f), RunHalfUnary(H::bits(4.0f), op)); CHECK_EQ(H::bits(1.0f), RunHalfUnary(H::bits(1.0f), op)); CHECK_EQ(H::bits(0.0f), RunHalfUnary(H::bits(0.0f), op)); CHECK_EQ(kFP16qNaN, RunHalfUnary(H::bits(-1.0f), op) & kFP16qNaN); } TEST_F(AssemblerRISCV64Test, RISCV_UTEST_fcvt_h_s) { if (!CpuFeatures::IsSupported(ZFH)) return; auto fn = [](MacroAssembler& assm) { __ fcvt_h_s(fa0, fa0); __ fmv_x_h(a0, fa0); }; CHECK_EQ(H::bits(1.0f), (GenAndRunTest(1.0f, fn))); CHECK_EQ(H::bits(-2.0f), (GenAndRunTest(-2.0f, fn))); CHECK_EQ(H::bits(0.0f), (GenAndRunTest